The invention relates generally to output buffer stages, and more particularly to input/output buffer stages that can withstand overvoltage conditions.
There is a constant challenge to continuously design smaller, faster and more complicated integrated circuits to provide increased functionality for multimedia applications and other applications. With the continued demand for higher speed and lower power consumption integrated circuits a need exists for simple, low cost and reliable over voltage protection circuits. Graphics controller chips, like many integrated circuit devices, utilize CMOS, logic cores, and associated I/O pads as part of their circuit makeup. I/O pads can include, for example, input/output buffers coupled to a common pad or pin. For example, CMOS based video graphics chips with 128 input/output ports (I/O ports) are required to operate at clock speeds of 125 MHz to 250 MHz or higher. Such devices may use a 2.5 V or 1.8 V power supplies for much of their logic to reduce power consumption. One way to increase the operating speed of such devices is to decrease the gate length of core circuitry transistors. However, a decrease in the gate length and gate oxide thickness of MOS devices can reduce safe operating voltage to lower levels.
For example, where an integrated circuit contains digital circuitry that operates from a 2.5 V source and is fabricated using silicon dioxide gate thickness of 50 Angstroms, a resulting safe operating voltage may be approximately 2.8 V. Such IC""s must often connect with more conventional digital devices that operate at 5 V or 3.3 V. A problem arises when the core logic circuitry (operating at 1.8 V) receives 5 V digital input signals from peripheral devices on input pins (or I/O pins). Such standard 5 V input signals or 3.3 V input signals can cause damage if suitable voltage protection is not incorporated.
As smaller gate oxide thicknesses are used to increase the speed and density of integrated circuits, transistors must withstand varying supply voltage operating ranges. For example, external circuits may provide 5 V input signals during normal operating modes. Although a combination of thick gate and thin gate devices can make it easier to design circuitry, it introduces another gate thickness and increases the number of processing steps required to fabricate the IC. This adds to the expense of the integrated circuit. In addition, dual gate oxide circuits such as those using 1.8 V or 3.3 V supply voltages typically cannot withstand a 5 V signal during normal operation.
Also, I/O buffers may receive an input signal of, for example, 5 V or more, on a same pin or pad that is connected to the output buffer stage. With smaller gate oxide thicknesses, the safe gate to drain and safe gate to source voltages decreases. Accordingly, traditional cascaded output buffer stages can be damaged when the I/O pin or pad receives an input signal that is much higher than an I/O pad supply voltage or a supply voltage to internal core circuitry. Also, conventional I/O buffers are tristated the output buffer stage when the I/O buffer is configured to receive data. These conventional I/O buffers typically have pull up or pull down circuits that are typically achieved using pmos transistor or cascaded nmos transistor configurations. Where voltage protection is provided, such as clamp diodes, unnecessary draw current can result when the pad is sent an input signal, such as 5 V, from another circuit for a continued length of time. In addition, cascaded configurations may be inadequate where signals that are being sent from the core through the buffer stage are at a lower level than the buffer stage supply voltage. The voltage difference may be such that an unsuitable threshold drop across a transistor gate to drain or gate to source paths are inadequate to properly shut off an output buffer circuit.
Conventional cascaded output buffers also typically use constant reference voltages for gates of the cascaded transistors. Moreover, with a 5 V input, and a much lower buffer supply voltage, for example, the constant voltage references need to be large enough to avoid gate to drain and gate to source overvoltages of the cascaded transistors. Also, for transmission or output of data from the output buffer, the drive strength of pull up circuits may not be strong enough due to the low supply voltages of either the core supply voltage or the I/O buffer supply voltage. In addition, it would be desirable to have a suitable output buffer stage that utilized single gate oxide elements to improve fabrication costs and wafer yields.
Accordingly, there exists a need to avoid excessive gate to source and gate to drain overvoltage conditions in cascaded stages of an output buffer.